Fujitsu MB90335 Series Hardware Manual page 152

MB90335 Series
■ Machine Clock
The PLL clock and main clock output from the PLL multiplying circuit are used as machine clocks. These
machine are clocks supplied to the CPU or peripheral function. One of the main and PLL modes can be
selected by writing the CKSCR of MCS bit.
Figure 5.4-1 shows the transition chart of the machine clock selection.
Figure 5.4-1 State Transition Diagram of Machine Clock Selection
(1)
MCS bit "0" write
(2)
PLL clock oscillation stabilization wait end & CS1, CS0=00
(3)
PLL clock oscillation stabilization wait end & CS1, CS0=01
(4)
PLL clock oscillation stabilization wait end & CS1, CS0=10
(5)
MCS bit "1" write (within Watchdog reset)
(6)
Synchronous timing of PLL clock and Main clock
MCS
MCM
CS1, CS0
Note:
The initial value for machine clock is the main clock (MCS = 1).
CM44-10137-6E
Main
MCS = 1
MCM = 1
CS1,CS0 = xx
(6)
(6)
(6)
(6)
: PLL clock selection bit of Clock selection register (CKSCR)
: PLL clock display bit of Clock selection register (CKSCR)
: Multiplication factor selection bit of Clock selection register (CKSCR)
FUJITSU MICROELECTRONICS LIMITED
(1)
(6)
(2)
Main → PLLx
(3)
MCS = 0
(4)
MCM = 1
CS1,CS0 = xx
PLL1 → Main
MCS = 1
MCM = 0
(5)
CS1,CS0 = 00
PLL2 → Main
MCS = 1
MCM = 0
(5)
CS1,CS0 = 01
PLL4 → Main
MCS = 1
MCM = 0
(5)
CS1,CS0 = 10
CHAPTER 5 CLOCK
5.4 Clock Mode
PLL1
multiplication
MCS = 0
MCM = 0
CS1,CS0 = 00
PLL2
multiplication
MCS = 0
MCM = 0
CS1,CS0 = 01
PLL4
multiplication
MCS = 0
MCM = 0
CS1,CS0 = 10
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