Fujitsu MB90335 Series Hardware Manual page 624

16-bit microcontroller
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Transmit Interrupt Generation and Flag Set Timing
.......................................................... 408
Flash Memory
All Data Erase from Flash Memory (Chip Erase)
Data Programming to Flash Memory
Detailed Explanation of Programming and Erasing Flash
.............................................. 501
Memory
Erasing Any Data in Flash Memory (Sector Erasing)
.......................................................... 506
Erasing Procedure for Flash Memory Sectors
Features of Dual Operation Flash Memory
List of Registers and Reset Values of Flash Memory
.......................................................... 480
Overview of Dual Operation Flash Memory
Programming and Erasing Flash Memory
Read/Reset State in Flash Memory
Sector and Bank Configuration of Dual Operation Flash
.............................................. 478
Memory
Flash Memory Control Status Register
Flash Memory Control Status Register (FMCS)
Flash Memory Write Control Register
Flash Memory Write Control Register (FWR0/FWR1)
.......................................................... 484
Flash Memory Write Control Register (FWR0/FWR1)
......................................... 487
Setting Flow
Flash Microcomputer Programmer
Example of Minimum Connection to Flash Microcomputer
Programmer (when Using User Power)
Flash Microcomputer Programmer System
Flash Microcomputer Programmer System
Flow
Flow of Patch Processing
FMCS
Flash Memory Control Status Register (FMCS)
.......................................... 488
Setting of FMCS:WE
FPT-64P-M23
Pin Assignment (FPT-64P-M23)
FRAME Setting Register
FRAME Setting Register (HFRAME)
Fujitsu Standard
Pins Used for Fujitsu Standard Serial On-Board
........................................ 515
Programming
Function
Type and Function of USB Interrupt
FWR
Flash Memory Write Control Register (FWR0/FWR1)
.......................................................... 484
Flash Memory Write Control Register (FWR0/FWR1)
......................................... 487
Setting Flow
G
General-purpose Register
General-purpose Registers
H
HADR
Host Address Register (HADR)
....... 505
....................... 503
............ 506
............... 476
.............. 476
................. 477
......................... 502
......... 481
....... 521
............... 517
...................................... 472
......... 481
................................ 9
..................... 267
......................... 51
...................................... 30
............................. 265
Handshake Packet
...............................................277
Handshake Packet
Hardware
Construction of Hardware Interrupt
Function of Hardware Interrupt
Hardware Interrupt Suppression
Initial Value of Hardware Component
Operation Flow of Hardware Interrupt
Operation of Hardware Interrupt
Procedure for Using a Hardware Interrupt
Return from Hardware Interrupt
Start of Hardware Interrupt
Hardware Interrupt
Hardware Interrupt Processing Time
Hardware Sequence
Hardware Sequence Flags
Hardwire
Hardwired Reset Vector Addresses
HCNT
Host Control Register 0, 1(HCNT0/HCNT1)
HEOF
EOF Setting Register (HEOF)
HERR
Host Error Status Register (HERR)
HFCOMP
SOF Interruption FRAME Comparison Register
...........................................263
(HFCOMP)
HFRAME
FRAME Setting Register (HFRAME)
HIRQ
Host Interruption Register (HIRQ)
HOST
..........................................244
Feature of USB HOST
.........................................247
Register of USB HOST
Restriction on USB HOST
Setting of HOST Function
UART Block Diagram of USB HOST
Host
.............................................236
Wake-up from Host
Host Address Register
Host Address Register (HADR)
Host Control Register
Host Control Register 0, 1(HCNT0/HCNT1)
Host Error Status Register
Host Error Status Register (HERR)
Host Interruption Register
Host Interruption Register (HIRQ)
Host State Status Register
Host State Status Register (HSTATE)
Host Token Endpoint Register
Host Token Endpoint Register (HTOKEN)
HRTIMER
Retry Timer Setting Register (HRTIMER)
HSTATE
Host State Status Register (HSTATE)
...........................60
................................59
................................60
......................355
........................64
...............................63
...................65
................................62
......................................62
..........................68
.....................................494
..........................493
.............250
................................266
..........................257
......................267
..........................254
.....................................245
.....................................271
......................246
..............................265
.............250
..........................257
..........................254
......................260
...............268
................264
......................260
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