Fujitsu MB90335 Series Hardware Manual page 210

MB90335 Series
Figure 10.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
[Block diagram of Watchdog timer]
[Minimum interval time]
Count clock a
2 divided value b
2 divided value c
Count enable
Reset signal d
[Maximum interval time]
Count clock a
2 divided value b
2 divided value c
Count enable
Reset signal d
CM44-10137-6E
2-bit counter
a
2 divided
Clock selector
circuit
Count enable
output circuit
WTE bit
When clear WTE bit immediately before rising of count clock
Count start
Counter clear
7
WTE bit clear
When clear WTE bit immediately after rising of count clock
Count start
Counter clear
(Count clock cycle/2)
9
WTE bit clear
FUJITSU MICROELECTRONICS LIMITED
10.4 Operations of Watchdog Timer
b
2 divided
circuit
Count enable and clear
(Count clock cycle/2)
Watchdog reset generation
Watchdog reset generation
CHAPTER 10 WATCHDOG TIMER
d
c
Reset
Reset circuit
signal
189