Fujitsu MB90335 Series Hardware Manual page 381

CHAPTER 16 DTP/EXTERNAL INTERRUPT
16.2 Register of DTP/External Interrupt
■ DTP/Interruption Factor Register (EIRR: External Interrupt Request Register)
Figure 16.2-3 shows the bit configuration of DTP/interruption factor register (EIRR).
Figure 16.2-3 Bit Configuration of DTP/interruption Factor Register (EIRR)
bit
EIRR
Address : 00003D
H
The DTP/interrupt factor register (EIRR) indicates the presence of corresponding external DTP/interrupt
request when reading and clears the flip-flop contents that indicates this request when writing. When "1" is
read from the EIRR register it indicates the external DTP/interrupt request presence in a pin corresponding
to the ERx bit. In addition, when "0" is written in the EIRR register, the request flip-flop of the
corresponding bit is cleared. Writing "1" causes no operation. "1" is read with a read-modify-write
instruction.
Notes:
• The initial value is "00
in the common-use with the external interrupt.
• Clear only the bits that the CPU accepted the interrupt (those bits that ER7 to ER0 are set to "1")
to "0" when plural external interrupt request outputs are enabled (ENIR: EN7 to EN0 = 1). No
other bits must be cleared unconditionally.
• The value of the DTP/external interrupt factor bit (EIRR:ER) is available only when the
corresponding DTP/external internal enable bit (ENIR:EN) is set to "1".
When the DTP/external interrupt is not enabled (ENIR:EN = 0), the DTP/external interrupt may be
set regardless of whether the DTP/external interrupt factor exists or not.
• Clear the corresponding DTP/external internal factor bit (ENIR:ER) just before enabling the DTP/
external interrupts (ENIR:EN = 1).
■ Request Level Setting Register (ELVR: External Level Register)
Figure 16.2-4 shows the bit configuration of the request level setting register (ELVR).
ELVR
Address : 00003E
Address : 00003F
The request level setting register (ELVR) selects the request detection level. Two bits are allocated per pin
as shown in Table 16.2-1. When the request input is in the level mode and the input is active, it is again set
even if it is cleared.
360
15 14 13 12
ER7 ER6 ER5 ER4
R/W R/W R/W R/W
" while the value is changed after the reset depending on the status of pin
H
Figure 16.2-4 Request Level Setting Register (ELVR)
7 6
bit
LB3 LA3
H
R/W R/W
15 14
bit
LB7 LA7
H
R/W R/W
FUJITSU MICROELECTRONICS LIMITED
11 10 9
ER3 ER2 ER1
R/W R/W R/W
5 4 3
LB2 LA2 LB1 LA1
R/W R/W R/W R/W
13 12 11
LB6 LA6 LB5 LA5
R/W R/W R/W R/W
MB90335 Series
8
Initial value
ER0
00000000
B
(However, the object is different
R/W
between both of them.)
2 1 0
Initial value
LB0 LA0
00000000
R/W R/W
10 9 8
Initial value
LB4 LA4
00000000
R/W R/W
B
B
CM44-10137-6E