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MB90335 Series
[bit13] PE10: ppg output Enable10 (PPG1/PPG3 output pin enabled)
Inhibition and permission of pulse output to the external pulse output pin PPG1/PPG3 are controlled.
PE10
0
1
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit12] PIE1: ppg Interrupt Enable (interrupt to PPG1/PPG3 enabled)
PPG1/PPG3 interrupt inhibition and permission are controlled.
PIE1
0
1
• If PUF1 is set to "1" when this bit is "1", an interrupt request is generated. When this bit is "0", no
interrupts are generated.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit11] PUF1: Ppg Underflow Flag (PPG1/PPG3 counter underflow)
Detected result of counter underflow of the PPG1/PPG3 is shown.
PUF1
0
1
In the 8-bit PPG 4channel mode (PPG0, PPG1/PPG2, PPG3) and the 8-bit prescaler + 8-bit PPG mode, the
counter values of ch.1, ch.3 are set to "1" when they underflow from 00
2 channel mode (PPG0, PPG1/PPG2, PPG3), the counter values of ch.1, ch.3/ch.0, ch.2 are set to "1" when
they underflow from 0000
significant. "1" is read with a read-modify-write instruction.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
CM44-10137-6E
General-purpose port pin (pulse output interdiction)
PPG1/PPG3 pulse output (pulse output permission)
The PPG counter underflow has not been detected.
The PPG counter underflow was detected.
to FFFF
. Becomes "0" by written "0". "1" writing in the PUF0 bit is not
H
H
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 15 8/16-BIT PPG TIMER
15.2 Registers of 8/16-bit PPG Timer
Operating State
Operating State
Disables the interrupt.
Interruption permission.
Operating State
to FF
. In the 16-bit PPG
H
H
347
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