Table of Contents
Advertisement
MB90335 Series
●
System clock generation circuit
Generates an oscillation clock (HCLK) using the oscillator connected to the high-speed oscillation pin. It is
also possible to input an external clock.
●
PLL multiplying circuit
The oscillation clock is multiplied by PLL oscillation and supplied to the CPU clock selector.
●
Clock selector
From the main clock, and the three PLL clocks, this selects the clock to be supplied to the CPU and
periphery clock control circuits.
●
Clock select register (CKSCR)
Switches between the oscillation and PLL clocks, selects the oscillation stabilization wait time, and selects
the PLL clock multiplier.
●
Oscillation stabilization wait time selector
A circuit which selects the oscillation stabilization wait time for the oscillation clock succeeding release of
the stop mode or a watchdog reset. Four time-base timer outputs are selected.
CM44-10137-6E
FUJITSU MICROELECTRONICS LIMITED
5.2 Block Diagram of Clock Generation Section
CHAPTER 5 CLOCK
127
Advertisement
Table of Contents
