Fujitsu MB90335 Series Hardware Manual page 15

18.4.4 Serial Input Data Register 0, 1 (SIDR0, SIDR1) and Serial Output Data Register 0, 1
(SODR0, SODR1) ..................................................................................................................... 400
18.4.5 UART Prescaler Control Register 0, 1 (UTCR0, UTCR1) and UART Prescaler Reload Register 0, 1
(UTRLR0, UTRLR1) .................................................................................................................. 402
18.5 UART Interrupt ................................................................................................................................ 404
18.5.1 Receive Interrupt Generation and Flag Set Timing ................................................................... 406
18.5.2 Transmit Interrupt Generation and Flag Set Timing .................................................................. 408
18.6 UART Baud Rate ............................................................................................................................ 410
18.6.1 Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator ................. 411
18.6.2 Baud Rate of the External Clock Using the Dedicated Baud Rate Generator ........................... 412
18.6.3 Baud Rate of the External Clock (One-to-one Mode) ................................................................ 413
18.7 Explanation of Operation of UART ................................................................................................. 414
18.7.1 Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode1) ............................ 416
18.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 419
18.7.3 Bidirectional Communication Function (Normal Mode) ............................................................. 422
18.7.4 Master/Slave Mode Communication Function (Multi-processor mode) ..................................... 424
18.8 Notes on Using UART .................................................................................................................... 427
18.9 Example of UART Programming .................................................................................................... 428
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CHAPTER 19 I C INTERFACE ....................................................................................... 431
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19.1 I C Interface Outline ....................................................................................................................... 432
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19.2 I C Interface Register ..................................................................................................................... 434
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19.2.1 I C Bus Status Register 0 (IBSR0) ............................................................................................ 435
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19.2.2 I C Bus Control Register 0 (IBCR0) .......................................................................................... 437
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19.2.3 I C Bus Clock Control Register 0 (ICCR0) ................................................................................ 443
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19.2.4 I C Bus Address Register 0 (IADR0) ......................................................................................... 445
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19.2.5 I C Bus Data Register 0 (IDAR0) .............................................................................................. 446
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19.3 I C Interface Operation ................................................................................................................... 447
19.3.1 Transfer Flow of I
19.3.2 Mode Flow of I
19.3.3 Operation Flow of I
CHAPTER 20 ROM MIRROR FUNCTION SELECTION MODULE ................................ 455
20.1 Overview of ROM Mirror Function Select Module .......................................................................... 456
20.2 ROM Mirror Function Select Register (ROMM) .............................................................................. 457
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ......................................... 459
21.1 Overview of Address Match Detection Function ............................................................................. 460
21.2 Block Diagram of Address Match Detection Function .................................................................... 461
21.3 Configuration of Address Match Detection Function ...................................................................... 462
21.3.1 Program Address Detection Control Status Register (PACSR) ................................................ 463
21.3.2 Program Address Detection Registers (PADR0, PADR1) ......................................................... 465
21.4 Explanation of Operation of Address Match Detection Function .................................................... 467
21.4.1 Example of Using Address Match Detection Function .............................................................. 468
21.5 Program Example of Address Match Detection Function ............................................................... 473
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C Interface ................................................................................................... 449
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C Interface ........................................................................................................ 451
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C Interface ................................................................................................. 452
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