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APPENDIX B Instructions
B.4 Indirect Addressing
●
Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
Before execution
After execution
●
Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
Before execution
After execution
548
an offset and stores it in A.)
A 0 7 1 6
2 5 3 4
RL2 F 3 8 2
4 B 0 2
A 2 5 3 4 F F E E
RL2 F 3 8 2
4 B 0 2
addressing with an offset and stores it in A.)
A 0 7 1 6
2 5 3 4
PCB C 5 PC 4 5 5 6
A 2 5 3 4
F F E E
PCB C 5 PC 4 5 5 A
FUJITSU MICROELECTRONICS LIMITED
(+25
)
Memory space
H
824B27
H
824B28
H
Memory space
C54556
7 3
H
C54557
9 E
H
C54558
2 0
H
C54559
0 0
H
C5455A
+4
H
.
.
+20
.
H
C5457A
E E
H
C5457B
F F
H
MB90335 Series
E E
F F
MOVW
H
A, @PC+20
CM44-10137-6E
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