Host Control Register 0,1(Hcnt0/Hcnt1) - Fujitsu MB90335 Series Hardware Manual

CHAPTER 12 USB HOST
12.4 Register of USB HOST
12.4.1

Host Control Register 0,1(HCNT0/HCNT1)

Host control registers 0,1(HCNT0/HCNT1) specify the USB operation mode and the
settings of an interrupt.
■ Host Control Register 0, 1(HCNT0/HCNT1)
Figure 12.4-1 Bit Configuration of Host Control Register 0, 1 (HCNT0/HCNT1)
Host control register 0
bit
Address: 0000C0
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
Host control register 1
bit
Address: 0000C1
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
[bit 15 to bit 11] Reserved
It is reserved bit.
Be sure to set this bit to "0".
[bit 10] SOFSTEP: SOF interrupt condition selection
It sets whether an interrupt due to SOF is generated every time SOF is executed. The interrupt is
enabled when the SOFIRE bit in host control register 0 (HCNT0) is "1".
When it is "0", the interrupt is generated via the setting of the SOF interrupt FRAME comparison
register (HFCOMP), and when it is "1", the interrupt is unconditionally generated every time SOF is
executed. However, the interruption is not generated at the first SOF token. It is not initialized with the
RST bit in the UDC control register (UDCC).
SOFSTEP
250
7 6 5
RWKIRE URIRE CMPIRE
(R/W) (R/W) (R/W)
(0) (0) (0)
( ) ( ) ( )
15 14 13
Reserved Reserved Reserved
(R/W) (R/W) (R/W)
(0) (0) (0)
( ) ( ) ( )
0 Interrupt is generated due to the setting of HFCOMP.
1 Interruption generation
FUJITSU MICROELECTRONICS LIMITED
4 3 2
CNNIRE DIRE SOFIRE
(R/W) (R/W) (R/W)
(0) (0) (0)
( ) ( ) ( )
12 11 10
Reserved Reserved SOFSTEP
(R/W) (R/W) (R/W)
(0) (0) (0)
( ) ( ) ( )
Operation mode
MB90335 Series
1 0
URST HOST HCNT0
(R/W) (R/W)
(0) (0)
❍
( )
( )
9 8
CANCEL RETRY HCNT1
(R/W) (R/W)
(0) (1)
( ) ( )
CM44-10137-6E