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CHAPTER 2 CPU
2.6 Registers
●
Zero flag (Z)
The Z flag is set to "1" when the operation result is all "0". Otherwise, Z flag is cleared to "0".
●
Overflow flag (V)
The V flag is set when an overflow of a signed value occurs as a result of operation execution. In other
cases, V flag is cleared to "0".
●
Carry flag (C)
The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution. In
other cases, C flag is cleared to "0".
■ Register Bank Pointer (RP)
As shown in Figure 2.6-8, the register bank pointer (RP) register indicates the relationship between the
general-purpose registers of the F
registers exist. Specifically, the RP register indicates the starting memory address of the currently used
register bank in the following conversion expression: [00180
of five bits can take a value between "00
000180
H
general-purpose registers if the banks are not in internal RAM. All RP registers are initialized to "0" by a
reset. An instruction may transfer an 8-bit immediate value to the RP register but, only the lower 5 bits of
that data are used.
Initial value
■ Interrupt Level Mask Register (ILM)
As described in Figure 2.6-9, the interrupt level mask register (ILM) consists of 3 bits, indicating the CPU
interrupt masking level. Only an interrupt request of which interrupt level is higher than that indicated by
these 3 bits will be accepted. Level 0 is the highest priority interrupt, and level 7 is the lowest priority
interrupt (see Table 2.6-1). Therefore, for an interrupt to be accepted, its level value must be smaller than
the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, a
subsequent interrupt of the same or lower level cannot be accepted. All ILMs are initialized to "0" by a
reset. An instruction may transfer an 8-bit immediate value to the ILM register, but only the lower 3 bits of
that data are used.
34
2
MC-16LX and the internal RAM addresses where the general-purpose
to 00037F
in the memory. Even within that range, however, the register banks cannot be used as
H
Figure 2.6-8 Register Bank Pointer (RP)
B4
B3
0
0
Figure 2.6-9 Interrupt Level Mask Register (ILM)
ILM2
Initial value
FUJITSU MICROELECTRONICS LIMITED
H
" and "1F
" and allocate the register banks at addresses from
H
H
B2
B1
0
0
ILM1
ILM0
0
0
0
MB90335 Series
+ (RP) × 10
]. The RP register that consists
H
B0
: RP
0
: ILM
CM44-10137-6E
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