Fujitsu MB90335 Series Hardware Manual page 251

CHAPTER 11 USB FUNCTION
11.4 Operation Explanation of USB Function
●
Command completion processing
The DRQI is set when the status stage toward OUT has been completed. It enters a CPU interrupt process
when the DRQO is set, confirms that the number of received data is 0, and clears the interrupt cause DRQO
and returns to the interrupted point to prepare for the next setup stage.
■ Each Register Operation when Write Command Responds
For GetDescripter and the class vender command
Figure 11.4-7 Each Register Operation when Write Command Responds
Host PC
SETUP
Device
Device
Host PC
DRQIIE
DRQI
DRQOIE
DRQO
SETP
●
Set-up processing
When the setup stage is received, DRQO is set. If the DRQO is set, CPU interrupt is raised and the SETP
flag is confirmed. It reads as many commands as necessary in the receive buffer if the DRQO is set (which
does not mean all eight bytes need to be read), decode the commands, performs setting tasks. It clears the
DRQI (the interrupt cause DRQI due to the initial value of "1") without writing data to the transmission
buffer to prepare for a 0-byte response in the status stage, and sets the DRQIIE to confirm the successful
completion of the status stage. It also clears the SETP flag and the DRQO interrupt cause before returning
from the interrupt to the interrupted point.
●
Data stage processing
The DRQO is set when the data stage toward OUT has been completed. It enters a CPU interrupt process
when the DRQO is set, and first, confirms SIZE of the EP0 status register, and then activates DMA as
many times as required for the received number of pieces of data or reads data from the receive buffer via
CPU read. Then, it clears the DRQO interrupt cause before returning from the interrupt to the interrupted
point.
●
Command completion processing
The DRQI is set when the status stage toward IN has been completed. It enters a CPU interrupt process
when the DRQI is set, and can confirm that the status stage has been successfully completed. Then, it clears
the DRQIIE interrupt enable before returning to the interrupted point.
230
Setup stage
DATA0 OUT
ACK
Command
read
Setup processing
FUJITSU MICROELECTRONICS LIMITED
Data stage
DATA0 OUT DATA1
ACK
Soft clear
DATA0
Soft clear
read
Next processing for
data stage
MB90335 Series
Status stage
IN ACK
ACK
DATA1
DATA1
Soft clear
read
Command
completed
processing
CM44-10137-6E