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MB90335 Series
■ Clock Mode
●
PLL clock mode
In PLL clock mode, the CPU and peripheral function operate on a PLL multiplying clock of oscillation
clock (HCLK).
Note:
When using USB HOST and the USB function, you need to set to the PLL clock mode.
●
Main clock mode
In main clock mode, the CPU and peripheral function operate on a clock with 2-frequency division of
oscillation clock (HCLK). In this mode, the PLL multiplying circuit stops.
Reference:
For the clock mode, see section "5.4 Clock Mode".
■ CPU Intermittent Operation Mode
The CPU intermittent mode operates the CPU intermittently and lowers the power consumption while
supplying the high-speed clock to the peripheral functions. The CPU intermittent operation mode is a mode
for supplying intermittent clock only to the CPU when it makes access to the registers, internal memory,
peripheral functions, or external devices.
■ Standby Mode
Standby mode reduces the power consumption by the low-power consumption control circuit which stops
clock supply to the CPU (sleep mode), stops clock supply to the CPU and peripheral functions (time-base
timer mode), or stops the oscillation clock (stop mode).
●
PLL sleep mode
The PLL sleep mode terminates the CPU operation clock in the PLL clock mode and operates components
except for CPU under the PLL clock.
●
Main sleep mode
The main sleep mode terminates the CPU operation clock in the main clock mode and operates components
except for the CPU under the main clock.
●
Time-base timer mode
The time-base timer mode terminates all the operations other than the oscillation clock, the time-base timer,
and the clock timer, terminating all the functions other than the time-base timer and the watch timer.
CM44-10137-6E
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1 Outline of Low-Power Consumption Mode
137
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