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MB90335 Series
Table 17.2-2 Example of Settings of the Communication Prescaler (SDCR)
Div
1
2
4
8
Initialized to "000
Shift clock includes five alternatives of internal shift clock and one alternative of external shift clock. The
external shifts. Please set neither "110
Providing shift operation for each instruction is also possible by defining SCOE=0 on clock selection and
operating the port sharing SCK pin.
[bit12] SIE: Serial I/0 Interrupt Enable (enabling serial I/O interrupt)
Serial I/O interrupt request is controlled as shown in the table below.
SIE
0
1
• This bit is initialized to "0" at reset.
• This bit can be read and written.
[bit11] SIR: Serial I/0 Interrupt Request (serial I/O interrupt request)
On completion of the serial data transfer, this bit is set to "1". And when this bit turns to "1" on interrupt
enabled (SIE= 1), an interrupt request to the CPU occurs. A clear condition is different according to the
MODE bit.
• When MODE bit is "0", it is cleared by writing "0" to SIR bit.
• When MODE bit is "1", it is cleared by writing to or reading SDR bit.
• Regardless of values of MODE bit, it is cleared by resetting or writing "1" to STOP bit.
• It is not significant to write "1".
• On reading read/modify/write instructions, "1" is read in all cases.
[bit10] BUSY (forwarding status display)
This bit indicates whether serial transfer is running or not.
BUSY
0
1
• This bit is initialized to "0" at reset.
• This bit can only be read.
CM44-10137-6E
(Machine clock)
MD
DIV3
DIV2
1
0
0
1
0
0
1
0
0
1
0
1
" by reset. Rewriting under forwarding is a interdiction.
B
" nor "111
B
Stop or serial data register R/W standby [Initial value]
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 17 EXTENDED I/O SERIAL INTERFACE
17.2 Register in Extended I/O Serial Interface
DIV1
DIV0
0
0
0
1
1
1
1
1
" to SMD2, SMD1, and SMD0.
B
Operation
Serial I/O interrupt disabled [Initial value]
Serial I/O interrupt enabled
Operation
State of serial transfer
Machine cycle
(Recommended Setting)
3 MHz
6 MHz
12 MHz
24 MHz
371
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