Table of Contents
Advertisement
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
21.3 Configuration of Address Match Detection Function
■ Functions of Program Address Detection Registers
• There are two Program address detection registers (PADR0, PADR1) that consist of a high byte (bank),
middle byte, and low byte, totaling 24 bits.
Table 21.3-2 Address Setting of Detect Address Setting Registers
Register Name
Program address detection
register 0
Program address detection
register 1
• In the Program address detection registers (PADR0, PADR1), starting address (first byte) of instruction
to be replaced by INT9 instruction should be set.
Figure 21.3-4 Setting of Starting Address of Instruction Code to be Replaced by INT9
Address
FF001C :
FF001F :
FF0022 :
Notes:
• When an address of other than the first byte is set to the Program address detection registers
(PADR0, PADR1), the instruction code is not replaced by INT9 instruction and a program of an
interrupt processing is not be performed. When the address is set to the second byte or
subsequent, the address set by the instruction code is replaced by "01
and, which may cause malfunction.
• The Program address detection registers (PADR0, PADR1) should be set after disabling the
address match detection (PACSR: AD0E = 0 or AD1E = 0) of corresponding address match
control registers. If the detect address setting registers are changed without disabling the address
match detection, the address match detection function will work immediately after an address
match occurs during writing address, which may cause malfunction.
• The address match detection function can be used only for addresses of the internal ROM area. If
addresses of the external memory area are set, the address match detection function will not work
and the INT9 instruction will not be executed.
466
Interrupt Output Enable
PACSR: AD0E
PACSR: AD1E
Set to detect address (High : FF
Instruction code
Mnemonic
A8 00 00
MOVW
4A 00 00
MOVW
4A 80 08
MOVW
FUJITSU MICROELECTRONICS LIMITED
Address Setting
High
Set the upper 8 bits of detect address 0 (bank).
Middle
Set the middle 8 bits of detect address 0.
Low
Set the lower 8 bits of detect address 0.
High
Set the upper 8 bits of detect address 1 (bank).
Middle
Set the middle 8 bits of detect address 1.
Low
Set the lower 8 bits of detect address 1.
, Middle : 00
H
RW0, #0000
A, #0000
A,#0880
MB90335 Series
, Low : 1F
)
H
H
" (INT9 instruction code)
H
CM44-10137-6E
Advertisement
Table of Contents
