Low-Voltage Detection Circuit; Figure 17.3 Operational Timing Of Power-On Reset Circuit - Renesas H8 Series Hardware Manual

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
t
PWON
Vcc
Vpor
RES
PSS-reset
signal
OVF
Internal reset
signal
PSS counter starts

Figure 17.3 Operational Timing of Power-On Reset Circuit

17.3.2

Low-Voltage Detection Circuit

(1) LVDR (Reset by Low Voltage Detection) Circuit:
Figure 17.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is kept
enabled during the LSI's operation.
When the power-supply voltage falls below the Vreset voltage (the value selected by the LVDSEL
bit: Typ. = 2.3 V or 3.6 V), the LVDR circuit clears the LVDRES signal to 0, and resets prescaler
S. The low-voltage detection reset state remains in place until a power-on reset is generated. When
the power-supply voltage rises above the Vreset voltage (Typ. = 3.6 V regardless of LVDSEL bit
setting) again, the LVDR circuit sets the LVDRES signal to 1 and prescaler S starts counting.
When 131,072 clock (φ) cycles have been counted, the internal reset signal is released. In this
case, the LVDSEL bit in LVDCR is initialized (the Vreset voltage: Typ. = 3.6 V).
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Rev. 1.00 Aug. 28, 2006 Page 296 of 400
REJ09B0268-0100
131,072 cycles
Reset released
Vss
Vss