HP StorageWorks MSA 2/8 - SAN Switch Reference Manual page 89

For V4.1.x, the default pattern used (by POST also) is a QUAD_RAMP with a
seed value of 0.
Subtest 3
The ASIC-to-ASIC connection subtest verifies that any port can read the data
from any of the ASICs in the switch; thus verifying both the logic transmitting and
receiving the data and the physical transmit data paths on the main board
connecting all the ASICs to each other.
Note:
The test method is as follows:
1. Fill the Central Memory of all ASICs with unique frames.
2. Set up the hardware such that each ASIC is read by all of the MAX number of
3. Repeat the steps above for the complemented pattern.
4. Repeat for each ASIC pair in the blade under test.
The pattern used is generated similarly as in subtest 2 above except that only 2112
bytes are generated.
Fabric OS Version 3.1.x/4.1.x Reference Guide
ASIC #3: 0xfff9d389, 0xfff9d388, 0xfff9d387, ...
ASIC #4: 0xfff8c609, 0xfff8c608, 0xfff8c607, ...
Subtest 3 is not available on 2 G based switches.
ports in the switch. Data received is compared against the frame written into
the ASIC.
— Port 0 reads the Central Memory in ASIC 0
— Port 1 reads the Central Memory in ASIC 0
— Port 14 reads the Central Memory in ASIC 0
— Port 15 reads the Central Memory in ASIC 0
— Port 0 reads the Central Memory in ASIC 1
— Port 1 reads the Central Memory in ASIC 1
— Port 14 reads the Central Memory in ASIC 1
— Port 15 reads the Central Memory in ASIC 1
— Port 15 reads the Central Memory in ASIC 2
— Port 15 reads the Central Memory in ASIC 3
centralMemoryTest
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