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8.3.2
Timer Control Status Registers (Low) (TMCSR0: L,
TMCSR1: L)
The timer control status registers (Low) (TMCSR0: L, TMCSR1: L) enables or disables
the timer operation, checks the generation of a software trigger or an underflow,
enables or disables an underflow interrupt, selects the reload mode, and sets the output
of the TOT pin.
I Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
Figure 8.3-4 Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
7
6
5
R/W R/W R/W R/W R/W R/W R/W
R/W
: Read/Write
: Reset value
: Refer to "8.3.1 Timer Control Status Registers High" about MOD0 (bit 7).
4
3
2
1
0
bit0
TRG
0
1
bit1
CNTE
0
1
bit2
UF
0
1
bit3
INTE
0
1
bit4
RELD
0
1
bit5
OUTL
0
1
bit6
OUTE
0
1
Reset value
0 0 0 0 0 0 0 0
B
Software trigger bit
No effect
After reload, starting-up count operation
Timer operation enable bit
Timer operation disabled
Timer operation enabled (waiting start-up trigger)
Under flow generating flag bit
Read
Without under flow
With under flow
Under flow interrupt enable bit
Under flow interrupt disabled
Under flow interrupt enabled
Reload select bit
One-shot mode
Reload mode
TOT pin output level select bit
One-shot mode
(RELD=0)
High rectangular wave output
during counting
Low rectangular wave output
during counting
TOT pin output enable bit
Register and pin support for channel
Pin function
TMCSR0
General purpose I/O port
General purpose I/O port General purpose I/O port
TOT output
TOT0
CHAPTER 8 16-bit reload timer
Write
Clear UF bit
No effect
Reloaad mode
(RELD=1)
Low toggle output at starting
reload timer
High toggle output at starting
reload timer
TMCSR1
TOT1
257
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