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CHAPTER 15 UART1
Table 15.3-4 Functions of Serial Status Register 1 (SSR1) (1/2)
bit8
bit9
bit10
bit11
bit12
bit13
442
bit name
TIE:
Enable or disable send interrupt.
Transmit interrupt
When set to "1": A receive interrupt request is issued when
request enable bit
data written to the serial output data register 1 (SODR1) is
sent to the transmit shift register (bit 11: TDRE = 1).
RIE:
Enable or disable receive data.
Receive interrupt request
When set to 1: A receive interrupt request is issued when
enable bit
receive data is loaded to the serial input data register 1
(SIDR1) (bit 12: RDRF = 1) or when a receive error occurs
(bit 15: PE = 1, bit 14: ORE = 1, or bit 13: FRE = 1).
BDS:
This bit sets the direction of serial data transfer.
Transfer direction select
When set to 0: Transfers data from least significant bit (LSB
bit
first)
When set to 1: Transfers data from most significant bit
(MSB first)
Note:
TDRE:
Show the status of the serial output data register 1.
Transmit data write flag
• This bit is cleared to "0" when send data is written to the
bit
• This bit is set to "1" when data is loaded to the send shift
• When a transmission interrupt is enabled (bit 8: TIE = 1), a
RDRF:
Show the status of the serial input data register 1 (SIDR1).
Receive data load flag bit
• This bit is set to "1" when receive data is loaded to the serial
• This bit is cleared to "0" when data is read from the SIDR1.
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
FRE:
Detect a framing error in receive data.
flaming error flag bit
• This bit is set to "1" when a framing error occurs.
• This bit is cleared when 0 is written to the receive error flag
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
• When the framing error flag bit is set (bit 13: FRE = 1), data
Function
At reading and writing data from and to the serial data
register, data is written to the serial output data register
(SODR1) and then the transfer direction select bit (BDS) is
rewritten to switch between the upper bits and the lower bits
of data. In this case the written data becomes invalid.
serial output register 1(SODR1).
register and transmission starts.
transmit interrupt request is issued when data written to the
serial output data register 1(SODR1) is transmitted to the
transmit shift register (bit 11: TDRE=1).
input register 1 (SIDR1).
interrupt request is issued when receive data is loaded to the
serial input data register 1 (SIDR1).
clear bit (SCR1 register bit 10: REC).
interrupt request is issued when a framing error occurs.
in the serial input data register 1 (SIDR1) is invalid.
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