Fujitsu MB90895 Series Hardware Manual page 266

CHAPTER 8 16-bit reload timer
I Operation at Underflow
When the start trigger is input, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit
timer register, starting decrementing in synchronization with the count clock.When the 16-bit timer register
(TMR) is decremented from "0000
• When an underflow occurs with an underflow interrupt enabled (TMCSR: INTE = 1), an underflow
interrupt is generated.
• The TMRLR operation when an underflow occurs is set by the reload select bit in the timer control
status register (TMCSR: RELD).
(One-shot mode (TMCSR: RELD = 0))
When an underflow occurs, the TMR count operation is stopped.When the next start trigger is input, the
value set in the TMRLR is reloaded in the TMR, starting the TMR count operation.
• In the one-shot mode, during the TMR count operation, a High-level or Low-level rectangular wave is
output from the TOT pin.
• The pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select
the level (High or Low) of the rectangular wave.
(Reload mode (TMCSR: RELD = 1))
When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count
operation.
• In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation.
• The pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select
the level (High or Low) of a toggle wave.
• The 16-bit reload timer can be used as an interval timer by using an underflow interrupt.
Table 8.1-2 Interval Time of 16-bit Reload Timer
Internal clock mode
Event count mode
T: Machine cycle
The values in Interval time and the parenthesized values are provided when the machine clock operates
at 16 MHz.
Reference: The 16-bit reload timer 1 can be used as the clock input source of the UART1 and the start
trigger of the A/D converter.
248
H
Count Clock
1
2 T (0.125µs)
3
2 T (0.5µs)
5
2 T (2.0µs)
3
2 T or more
" to "FFFF ", an underflow occurs.
H
Count Clock Cycle Interval Time
0.125µs to 8.192ms
0.5µs to 32.768ms
2.0µs to 131.1ms
0.5µs or more