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3.5.9
Software interrupt ......................................................................................................................... 77
3.5.10
2
3.5.11
OS descriptor (ISD) ................................................................................................................. 80
3.5.12
3.5.13
3.5.14
2
3.5.15
OS Processing Time................................................................................................................ 87
3.5.16
Exception Processing Interrupt..................................................................................................... 89
3.5.17
Time Required to Start Interrupt Processing ................................................................................ 90
3.5.18
Stack Operation for Interrupt Processing ..................................................................................... 92
3.5.19
Program Example of Interrupt Processing.................................................................................... 93
3.6
Reset ................................................................................................................................................. 96
3.6.1
Reset Factors and Oscillation Stabilization Wait Times ............................................................... 98
3.6.2
External Reset Pin ...................................................................................................................... 100
3.6.3
Reset Operation ......................................................................................................................... 101
3.6.4
Reset Factor Bit .......................................................................................................................... 103
3.6.5
State of Each Pin at Reset ......................................................................................................... 106
3.7
Clock................................................................................................................................................ 107
3.7.1
Block Diagram of Clock Generation Section .............................................................................. 110
3.7.2
Register in Clock Generation Section......................................................................................... 112
3.7.3
Clock select register (CKSCR) ................................................................................................... 113
3.7.4
PLL/subclock control register (PSCCR) ..................................................................................... 116
3.7.5
Clock Mode................................................................................................................................. 118
3.7.6
Oscillation Stabilization Wait Time ............................................................................................. 122
3.7.7
Connection of Oscillator and External Clock .............................................................................. 123
3.8
Low-power Consumption Mode ....................................................................................................... 124
3.8.1
Block Diagram of Low-power Consumption Circuit .................................................................... 127
3.8.2
Registers for Setting Low-power Consumption Modes .............................................................. 129
3.8.3
Low-power consumption mode control register (LPMCR) .......................................................... 130
3.8.4
CPU Intermittent operation mode ............................................................................................... 133
3.8.5
Standby Mode ............................................................................................................................ 134
3.8.6
State Transition in Standby Mode .............................................................................................. 145
3.8.7
Pin State in Standby Mode, at Reset.......................................................................................... 146
3.8.8
Precautions when Using Low-power Consumption Mode .......................................................... 147
3.9
CPU Mode ....................................................................................................................................... 151
3.9.1
Mode Pins (MD2 to MD0) ................................................................................................................ 152
3.9.2
Mode Data ....................................................................................................................................... 154
3.9.3
Memory Access Mode ..................................................................................................................... 156
3.9.4
Operations for Selecting Memory Access Mode.............................................................................. 157
I/O PORT ................................................................................................... 159
4.1
Overview of I/O Ports....................................................................................................................... 160
4.2
Registers of I/O Port and Assignment of Pins Serving as External Bus .......................................... 161
4.3
Port 1 ............................................................................................................................................... 162
4.3.1
Registers for Port 1 (PDR1, DDR1) ............................................................................................ 164
4.3.2
Operation of Port 1 ..................................................................................................................... 165
4.4
Port2 ................................................................................................................................................ 167
2
OS Descriptor (ISD) ..................................................................................... 82
2
OS....................................................................................................................... 85
2
OS ......................................................................................................... 86
2
OS) .................................................................. 78
viii
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