Block Diagram Of 8-/16-Bit Ppg Timer 1 - Fujitsu MB90895 Series Hardware Manual

CHAPTER 10 8/16-bit PPG timer
10.2.2

Block Diagram of 8-/16-bit PPG Timer 1

The 8-/16-bit PPG timer 1 consists of the following blocks.
I Block Diagram of 8-/16-bit PPG Timer 1
PPG1 reload
register
Operating
mode control signal
Count starting
value
PPG1 under flow
(to PPG0)
PPG0 under flow
(from PPG0)
- : Unused
Reserved : Reserved bit
HCLK : Oscillation clock frequency
φ
: Machine clock frequency
* : The interrupt output of 8-/16-bit PPG timer 1 is combined to one interrupt by
OR circuit with the interrupt request output of PPG timer 0.
296
Figure 10.2-3 Block Diagram of 8-/16-bit PPG Timer 1
PRLH1 PRLL1
("H" side) ("L" side)
PPG1 temporary
buffer (PRLBH1)
Reload selector
L/H selector
Reload
Under
flow
PPG1 down counter
(PCNT1)
CLK
Time base timer output
(512/HCLK)
Peripheral clock (1/φ)
Peripheral clock (2/φ)
Peripheral clock (4/φ)
Peripheral clock (8/φ)
Peripheral clock (16/φ)
PPG1 operating mode control register
(PPGC1)
PEN1 - PE1 PIE1 PUF1 MD1 MD0
2
Select signal
Clear
PPG1
output latch
Inversion
PPG output control circuit
MD0
Count
3
clock
Select signal
selector
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
PPG0/1 count clock select register (PPG01)
"H" side data bus
"L" side data bus
Reserved
Interrupt
request
R
*
output
S Q
Pin
PPG1
- -