Transmit Complete Interrupt Enable Register (Tier) - Fujitsu MB90895 Series Hardware Manual

16.3.13

Transmit complete interrupt enable register (TIER)

The transmission complete interrupt enable register (TIER) enables or disables a
transmit complete interrupt for each message buffer.
I Transmit complete interrupt enable register (TIER)
Figure 16.3-21 Transmit complete interrupt enable register (TIER)
7 6
R/W R/W
R/W : Read/Write
5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W
:
Reset value
Reset value
0 0 0 0 0 0 0 0
B
bit0
Transmission interrupt enable bit 0
TIE0
(message buffer 0)
Transmission complete interrupt disabled
0
1 Transmission complete interrupt enable
bit1
Transmission interrupt enable bit 1
TIE1
(message buffer 1)
Transmission complete interrupt disabled
0
1 Transmission complete interrupt enable
bit2
Transmission interrupt enable bit 2
TIE2
(message buffer 2)
Transmission complete interrupt disabled
0
1 Transmission complete interrupt enable
bit3
Transmission interrupt enable bit 3
TIE3
(message buffer 3)
Transmission complete interrupt disabled
0
1 Transmission complete interrupt enable
bit4
Transmission interrupt enable bit 4
TIE4
(message buffer 4)
Transmission complete interrupt disabled
0
1 Transmission complete interrupt enable
bit5
Transmission interrupt enable bit 5
TIE5
(message buffer 5)
Transmission complete interrupt disabled
0
Transmission complete interrupt enable
1
bit6
Transmission interrupt enable bit 6
TIE6
(message buffer 6)
Transmission complete interrupt disabled
0
1 Transmission complete interrupt enable
bit7
Transmission interrupt enable bit 7
TIE7
(message buffer 7)
Transmission complete interrupt disabled
0
1 Transmission complete interrupt enable
CHAPTER 16 CAN controller
513