Fujitsu MB90895 Series Hardware Manual page 154

CHAPTER 3 CPU
3.8.5.1 Sleep Mode
The sleep mode stops the operating clock to the CPU during an operation in each clock
mode.The CPU stops and the resources continue to operate.
I Transition to Sleep Mode
When the mode transits to the sleep mode by setting the low-power consumption mode control register
(LPMCR: SLP = 1, STP = 0), the mode transits to the sleep mode according to the settings of the MCS and
SCS bits in the clock select register (CKSCR).
Table 3.8-4 shows the settings of the MCS and SCS bits in the clock select register (CKSCR) and the sleep
modes.
Table 3.8-4 Clock select register (CKSCR) settings and sleep modes
Clock select register (CKSCR)
Notes: • If both the STP and SLP bits in the low-power consumption mode control register
(LPMCR) are set to "1" simultaneously, the STP bit is preferred and the mode transits to
the stop mode.When the SLP and TMD bits are set to "1" and "0", respectively, at the
same time, the TMD bit supersedes the SLP bit, causing a transition to the timebase timer
mode or watch mode.
• There is no sub-clock in MB90F897S.
G
Data retention function
In the sleep mode, data in the dedicated registers such as accumulators and internal RAM are held.
G
Operation when interrupt request generated
If an interrupt request is generated when the SLP bit in the low-power consumption mode control register
(LPMCR) is set to "1", the mode does not transit to the sleep mode.If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed.If the CPU is ready
to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing
routine.
G
Pin state
In the sleep mode, pins other than those used for bus input/output or bus control are held in the state before
transiting to the sleep mode.
136
MCS SCS
1 1
0 1
1 0
0 0
Sleep Mode to be transited
Main sleep mode
PLL sleep mode
Sub-sleep mode