A/D Data Register (High) (Adcr: H) - Fujitsu MB90895 Series Hardware Manual

CHAPTER 13 8/10-bit A/D converter
13.3.3

A/D Data Register (High) (ADCR: H)

The higher five bits in the A/D data register (ADCR: H) select the compare time,
sampling time and resolution of A/D conversion.
Bits 9 and 8 in the A/D data register (ADCR) are explained in Section 13.3-4 A/D Data
Register (Low) (ADCR: L).
I A/D Data Register (High) (ADCR: H)
15 13
14
W W W
R : Read only
W : Write only
: Undefined
X
- : Unused
φ
: Machine clock
: Reset value
362
Figure 13.3-4 A/D Data Register (High) (ADCR: H)
12 11 10 9 8
*3 *3
W W - R R
bit12
CT1
0
0
1
1
bit14 bit13
ST1
0
0
1
1
bit15
S10
0
1
*1: The parenthesized values are provided when the machine clock
operates at 8-MHz
*2: The parenthesized values are provided when the machine clock
operates at 16-MHz
*3: Bit8 and bit9 are described in "A/D data register lower (ADCR: L)".
Reset value
00101XXX
B
bit11
CT0 Compare time select bit
φ µ
*1
0
44/ (5.5 s)
φ µ
*2
1 66/ (4.12 s)
φ µ
0 *2
88/ (5.5 s)
φ µ
*2
1
176/ (11.0 s)
Sampling time select bit
ST0
φ µ
*1
20/ (2.5 s)
0
φ µ
*2
32/ (2.0 s)
1
φ µ
*2
48/ (3.0 s)
0
φ µ
*2
128/ (8.0 s)
1
Resolution select bit
10 bits (D9 to D0)
8 bits (D7 to D0)