Interrupt Of Uart0 - Fujitsu MB90895 Series Hardware Manual

14.4

Interrupt of UART0

The UART0 has reception and transmission interrupts and can generate interrupt
requests in the following events.
• Receive data is loaded to the serial input data register 0 (SIDR0).
• A receive error (parity error, overrun error, framing error) occurs.
• When data to transmit is transferred from serial output data register 0 (SODR0) to the
transmission shift register.
These are ready for expanded intelligent I/O service (EI
I Interrupt of UART0
The UART0 interrupt control bits and interrupt factors are shown in Table 14.4-1.
Table 14.4-1 UART0 Interrupt Control Bit and Interrupt Factor
Trans-
missio
n/
Recep
tion
Recepti
on
Transm
ission
: using bit
×
: Unused bit
Operating
Interrupt mode
request
flag bit
0 1 2
SSR0:
RDRF
SSR0:ORE
×
SSR0:FRE
× ×
SSR0:PE
SSR0:
TDRE
2
OS).
Interrupt
Interrupt Factor factor enable
Receive data loaded
into serial input data
register 0 (SIDR0)
Overrun error
SSR0: RIE
Framing error
generating parity
error
Serial output data
register 0 (SODR) SSR0: TIE
is empty.
CHAPTER 14 UART0
Clear of the
Interrupt-
bit request Flag
Reading receive
data
Writing "0" to
the reception
error flag clear
bit (SSR0: REC)
Writing transmit
data
399