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CHAPTER 14 UART0
I List of Registers in UART0
Serial control register (SCR0)
Serial mode register (SMR0)
Serial status register (SSR0)
Serial input data register (SIDR0)
/serial output data register (SODR0)
Note : Function as SIDR0 when reading, function as SODR0 when writing
Serial edge select register (SES0)
Communication prescaler control
register (CDCR0)
: Undefined
I Interrupt Request Generation by UART0
G
Reception Interrupt
• When received data is loaded into the serial input data register (SIDR0), the receive data load flag bit
(SSR0: RDRF) in the serial status register is set to "1".When reception interrupts have been enabled
(SSR0: RIE = 1), a reception interrupt request is generated.
• When either a framing error, overrun error, or parity error occurs, the framing error flag bit (SSR0:
FRE), the overrun error flag bit (SSR0: ORE), or parity error flag bit (SSR0: PE) in the serial status
register are set to "1" according to the error occurred. When reception interrupts have been enabled
(SSR0: RIE = 1), a reception interrupt request is generated.
G
Transmission Interrupt
The transmit data empty flag bit (SSR0: TDRE) in the serial status register is set to "1" when data to
transmit is transferred from the serial output data register (SODR0) to the transmission shift
register.Interrupt requests are generated while transmission interrupts are enabled (SSR0: TIE = 1).
388
Figure 14.3-1 List of Registers and Reset Values in UART0
bit
15
14
13
12
0
0
0
0
bit
7
6
5
0
0
0
0
bit
15
14
13
12
0
0
0
0
bit
7
6
5
bit
15
14
13
12
bit
7
6
5
0
11
10
9
8
0
1
0
0
4
3
2
1
0
0
0
0
0
11
10
9
8
1
0
0
4
3
2
1
0
11
10
9
8
0
4
3
2
1
0
1
1
1
1
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