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CHAPTER 15 UART1
15.7
Precautions when Using UART1
Use of the UART1 requires the following precautions.
I Precautions when Using UART1
G
Enabling sending and receiving
The send enable bit (SCR1 register bit 8: TXE) and receive enable bit (SCR1 register bit 9: RXE) are
provided for sending and receiving.
• In the initial state after reset, both sending and receiving are disabled (SCR1 register bit 8: TXE = 0, bit
9: RXE = 0). Therefore, it is necessary to enable sending and receiving.
• Sending and receiving are disabled to stop (SCR1 register bit 8: TXE = 0, bit 9: RXE = 0).
G
Setting operation mode
Set the operation mode after disabling sending and receiving (SCR1 register bit 8: TXE = 0, bit 9: RXE =
0). When the operation mode is changed during transmission or reception, the transmitted/received data is
not guaranteed.
G
Clock synchronous mode
Operation mode 2 (clock synchronous mode) is set as the clock synchronous mode.Send and receive data
do not have start and stop bits.
G
Timing of enabling send interrupt
The initial value after reset of the send data write flag bit (SSR1 register bit 11: TDRE) is set at "1" (no
send data, send data write enabled). Therefore, the send interrupt is enabled (SSR1 register bit 8: TIE = 1)
and a send interrupt request is issued. Always prepare send data and enable a send interrupt (SSR1 register
bit 8: TIE = 1).
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