Table of Contents
Advertisement
CHAPTER 5 Timebase timer
5.6
Precautions when Using Timebase Timer
Precautions when using the timebase timer are shown below.
I Precautions when Using Timebase Timer
G
Clearing interrupt request
To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF = 0),
disable interrupts (TBTC: TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask
register in the processor status.
G
Clearing timebase timer counter
Clearing the timebase timer counter affects the following operations:
• When the timebase timer is used as the interval timer (interval interrupt).
• When the watchdog timer is used.
• When the clock supplied from the timebase timer is used as the operation clock of the PPG timer.
G
Using timebase timer as oscillation stabilization wait time timer
• After power on or in the main stop mode, PLL stop mode, and sub clock mode, the oscillation clock
stops.Therefore, when oscillation starts, the timebase timer requires the oscillation stabilization wait
time of the main clock. An appropriate oscillation stabilization wait time must be selected according to
the types of oscillators connected to high-speed oscillation input pins.
Reference:
For details on the oscillation stabilization wait time, see 3.7.6 Oscillation Stabilization Wait
Time.
G
Resources to which timebase timer supplies clock
• At transition to operation modes (PLL stop mode, sub clock mode, and main stop mode) in which the
oscillation clock stops, the timebase timer counter is cleared and the timebase timer stops.
• When the timebase timer counter is cleared, an after-clearing interval time is needed. It may cause the
clock supplied from the timebase timer to have a short High level or a 1/2 cycle longer Low level.
• The watchdog timer performs normal counting because the watchdog timer counter and timebase timer
counter are cleared simultaneously.
204
Advertisement
Table of Contents
