Fujitsu MB90895 Series Hardware Manual page 220

CHAPTER 5 Timebase timer
I Operation as Oscillation Stabilization Wait Time Timer
The timebase timer can be used as the oscillation stabilization wait timer for the main clock and PLL clock.
• The oscillation stabilization wait time is the time elapsed from when the timebase timer counter
increments from "0" until the set oscillation stabilization wait time select bit overflows (carrying).
Table 5.5-1 shows clearing conditions and oscillation stabilization wait time of timebase timer
Table 5.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer
(1/2)
Writing "0" to timebase timer
counter clear bit (TBTC: T BR)
Reset
Power on reset
watchdog reset
External reset
Software reset
Switching Clock Mode
Main clock
(CKSCR: MCS=1
Main clock
(CKSCR: SCS=1
Sub clock
(CKSCR: SCS=0
Sub clock
(CKSCR: MCS=0, SCS=0
PLL clock
(CKSCR: MCS=0
PLL clock
(CKSCR: MCS=0, SCS=1
Cancellation of stop modes
Cancellation of main stop mode
Cancellation of sub-stop mode
202
Operation
→
PLL clock
→
0)
→
sub clock
→
0)
→
main clock
→
1)
→
PLL clock
→
1)
→
main clock
→
1)
→
sub clock
→
0)
Counter TBOF Oscillation Stabilization Wait
Clear Clear
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
×
None
×
None
×
None
Transition to PLL clock mode after
oscillation stabilization wait time of
PLL clock completed
Transition to sub clock mode after
× ×
oscillation stabilization wait time of
sub clock completed
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
Transition to PLL clock mode after
oscillation stabilization wait time of
main clock completed
None
× ×
None
× ×
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
Transition to sub clock mode after
× ×
oscillation stabilization wait time of
sub clock completed
Time