Direct Page Register (Dpr) - Fujitsu MB90895 Series Hardware Manual

CHAPTER 3 CPU
3.2.6

Direct page register (DPR)

The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the
low address directly specified using the operand when executing the instruction by the
abbreviated direct addressing.
I Direct page register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the low address
directly specified using the operand when executing the instruction by the abbreviated direct addressing.
The direct page register (DPR) is 8 bits long and is set to "01
Figure 3.2-16 Generation of Physical Address in Direct Page Register (DPR)
DTB register
A A A A A A A A
24bit
Physical address
MSB Most significant bit
LSB Least significant bit
Figure 3.2-17 shows the setting of direct page register (DPR) and an example of data access.
Figure 3.2-17 Setting of Direct Page Register (DPR) and Data Access Example
MOV S:56
DTB register
DPR resister
MSB Most significant bit
LSB Least significant bit
46
MSB
A A A A A A A A
bit24 bit16 bit15
#5A
H H
12
H
34
H
" at a reset. It is a read and write register.
H
DPR register
B B B B B B B B
B B B B B B B B C C C C C C C C
bit8 bit7
Result of executing instruction
Upper 8bit Lower 8bit
123455
H
123457
H
123459
H
MSB
Direct addres during instruction
C C C C C C C C
LSB
bit0
123454
5A 123456
H
123458
LSB
H
H
H