Fujitsu MB90895 Series Hardware Manual page 143

I Clock Mode
G
PLL clock mode
In PLL clock mode, the CPU and peripherals operate on a PLL multiplying clock of oscillation clock
(HCLK).
G
Main clock mode
In main clock mode, the CPU and peripherals operate on a clock with 2-frequency division of oscillation
clock (HCLK). In this mode, the PLL multiplying circuit stops.
G
Sub clock mode
In sub clock mode, the CPU and peripherals operate on a sub clock (SCLK).In this mode, the main clock
and PLL multiplying circuit stop.The sub clock oscillation stabilization wait time (approximately 2 s) is
generated at power on or at cancellation of the stop mode.If the clock mode is switched from main clock
mode to subclock mode, therefore, the oscillation stabilization wait time is generated.
Note: There is no sub-clock in MB90F897S.
Note: For the clock mode, see 3.7 "Clocks".
I CPU Intermittent operation mode
In CPU intermittent operation mode, the CPU performs the intermittent operation with the high-speed clock
supplied to the peripherals to reduce the power consumption.In this mode, the intermittent clock is input to
only the CPU at accessing registers, internal memory, resources, or at the external access.
I Standby Mode
The standby mode causes the standby control circuit to stop the supply of an operation clock to the CPU or
peripherals or to stop the oscillation clock (HCLK) in order to reduce power consumption.
G
Sleep mode
The sleep mode stops supply of an operation clock to the CPU during operation in each clock mode.The
CPU stops and the peripherals operate in the clock mode before the transition to the sleep mode.The sleep
mode is divided into the main sleep mode, PLL sleep mode, and sub-sleep mode according to the clock
mode before the transition to the sleep mode.
G
Watch mode
The watch mode operates only the sub clock (SCLK) and watch timer.The main clock and PLL clock
stop.All peripherals except the watch timer stop.
CHAPTER 3 CPU
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