Fujitsu MB90895 Series Hardware Manual page 161

Note: To set that pin to high impedance which serves either as a peripheral resource or as a port in
stop mode, disable the output of the peripheral resource, then set the STP bit of to "1".Listed
below are applicable ports.
This applies to the following pins: P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0,
P23/TOT1
Return from Stop Mode
The stop mode is cancelled by a reset factor or when an interrupt is generated.At return from the stop mode,
the oscillation clock (HCLK) stops and the sub clock (SCLK), so the stop mode is cancelled after the elapse
of the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time.
Return by reset factor
When the stop mode is cancelled by a reset factor, the main clock oscillation stabilization wait time is
generated.After the termination of the main clock oscillation stabilization wait time, the stop mode is
cancelled, transiting to the reset sequence.
Figure 3.8-7 shows the return from the sub-stop mode by an external reset.
Figure 3.8-7 Return from the Sub-stop Mode by an External Reset
RST pin
Stop mode
Main clock
Subclock
PLL clock
CPU operation clock
CPU clock
Notes: • To return from stop mode to main clock mode using the external reset pin (RST pin),
input the Low level for at least oscillator's oscillation time* + 100 µs + 16 machine
cycles (main clock).
*:The oscillation time for the oscillator is the period of time taken until its amplitude reaches
90%.
It takes several to dozens of ms for crystal oscillators, hundreds of µs to several ms for
FAR/ceramic oscillators, and 0 ms for external clocks.
• There is no sub-clock in MB90F897S.
Oscillation stabilization wait
Oscillation stabilization wait
Subclock
During stop Reset sequence
Cancellation of stop mode
Cancellation of reset
During oscillation
During oscillation
Oscillation
During oscillation
stabilization wait
Main clock PLL clock
Normal process
CHAPTER 3 CPU
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