Fujitsu MB90895 Series Hardware Manual page 698

APPENDIX
Table B-1 Register Index (4/10)
Register
Address Abbrevia
tion
000080
BVALR Message buffer validating register (BVALR)
H
000081
H
000082
TREQR Transmission complete register
H
000083
H
000084
TCANR Transmit cancel register (TCANR)
H
000085
H
000086
TCR Transmit complete register (TCR)
H
000087
H
000088
RCR Reception complete register
H
000089
H
00008A
RRTRR Reception RTR register
H
00008B
H
00008C
ROVRR Reception overrun register
H
00008D
H
00008E
RIER Reception complete interrupt enable register
H
00008F
H
to
00009D
H
00009E
PACSR Address detection control register
H
Delayed interrupt request generate/cancel
00009F
DIRR
H
register
Low-power consumption mode control
0000A0
LPMCR
H
register
0000A1
CKSCR Clock select register
H
0000A2
PILR port input level select register
H
0000A3
H
to
0000A7
H
0000A8
WDTC Watchdog timer control register
H
0000A9
TBTC Timebase timer control register
H
0000AA
WTC Watch timer control register
H
680
Register Name
(Reserved area)
(Reserved area)
(Reserved area)
(Reserved area)
(Reserved area)
(Reserved area)
(Reserved area)
(Reserved area)
(Reserved area)
Reset Value Resource Name
00000000
CAN controller
B
*
00000000
CAN controller
B
*
00000000
CAN controller
B
*
00000000
CAN controller
B
*
00000000
CAN controller
B
*
00000000
CAN controller
B
*
00000000
CAN controller
B
*
00000000
CAN controller
B
*
Address match
00000000
B
detecting function
Delayed interrupt
XXXXXXX0
B
generation module
Low-power
00011000
B
Consumption Mode
11111100
Clock
B
0000000X
I/O
B
*
XXXXX111
Watchdog timer
B
1XX00100
Timebase timer
B
1X001000
Watch timer
B
Page
Number
499
503
509
511
515
517
519
521
559
325
130
113
190
212
197
283