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Figure 3.5-3 Interrupt Control Register (ICR00 to ICR15) at Read
At read
6
7
5
4
3
2
-
-
R
R
R/W
R/W
R/W: Read/Write
W: Write only
- : Unused
X: Undefined
: Reset value
0
1
Reset value
X X 0 0 0 1 1 1
R/W
R/W
bit0
bit2
bit1
IL2
IL1
IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
bit3
ISE
0
When an interrupt occurs, start normal interrupt process
1
When an interrupt occurs, start El
bit5
bit4
S1
S0
0
0
When EI
0
1
Stop state by end of counting
1
0
Reserved
1
1
Stop state by request from resource
B
Interupt level setting bit
Interrupt level 0 (highest)
Interrupt level 7 (without interruption)
2
El
OS enable bit
2
OS
2
El
OS status bit
2
OS in operation or not started
CHAPTER 3 CPU
65
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