Fujitsu MB90895 Series Hardware Manual page 322

16 bit, controller manual
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CHAPTER 10 8/16-bit PPG timer
Table 10.3-3 Functions of PPG1 Operation Mode Control Register (PPGC1)
bit8
bit9
bit10
bit11
bit12
bit13
bit14
bit15
304
bit name
Reserved: reserved bit
Always set this bit to "1".
MD1, MD0:
These bits set the operation mode of the 8-/16-bit PPG timer.
Operation mode select
(Any mode other than 8-bit PPG output 2-channel
bits
independent operation mode)
• Use a word instruction to set the PPG operation enable bits
• Do not set operation of only one of the two channels (PEN1 =
Note:
PUF1:
8-bit PPG output 2-channel independent operation mode,
Underflow generation
8+8-bit PPG output operation mode: When the value of the
flag bit
PPG1 down counter is decremented from "00
an underflow occurs (PUF1 = 1).
16-bit PPG output operation mode: When the values of the
PPG0 and PPG1 down counters are decremented from
"0000
• When an underflow occurs (PUF1 = 1) with an underflow
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read by read modify write instructions: "1" read
PIE1:
This bit enables or disables an interrupt.
Underflow interrupt
When set to 0: No interrupt request is generated even at
enable bit
underflow (PUF1 = 1)
When set to 1: Interrupt request is generated at underflow
(PUF1 = 1)
PE1:
This bit switches the PPG1 pin function to enable or disable the
PPG1 Pin output enable
pulse output.
bit
When set to 0: Functions as general-purpose I/O port
The pulse output is disabled.
When set to 1: PPG0 pin functions as PPG0 output pin.The
pulse output is enabled.
Unused bits
Read: The value is undefined.
Write: No effect
PEN1:
This bit enables or disables the count operation of the 8-/16-bit
PPG1 operation enable
PPG timer 1.
bit
When set to 0: Count operation disabled
When set to 1: Count operation enabled
• When the count operation is disabled (PEN1 = 0), the output
Function
(PEN0 and PEN1) at one time.
0/PEN0 = 1 or PEN1 = 1/PEN0 = 0).
Do not set the MD1 and MD0 bits to "10
" to "FFFF
", an underflow occurs (PUF1 = 1).
H
H
interrupt enabled (PIE1 = 1), an interrupt request is generated.
is held at a Low level.
".
B
" to "FF
",
H
H

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