Fujitsu MB90895 Series Hardware Manual page 153

CHAPTER 3 CPU
: operation, : stop, : held in the state before transiting, Hi-Z: High impedance
*1: The timebase timer and watch timer operate.-
*2: The watch timer operates.
*3: The DTP/external interrupt input pin operates.
*4: Watch timer, timebase timer, and external interrupts
*5: Watch timer and external interrupts
*6: External interrupt INT6/INT7
MCS: PLL clock select bit in clock select register (CKSCR)
SCS: subclock select bit in the clock select register (CKSCR)
SPL: setting pin state bit of low-power consumption mode control register (LPMCR)
SLP: sleep mode bit of low-power consumption mode control register (LPMCR)
STP: stop mode bit of low-power consumption mode control register (LPMCR)
TMD: clock mode bit of low-power consumption mode control register (LPMCR)
Note: There is no sub-clock in MB90F897S.
135