Fujitsu MB90895 Series Hardware Manual page 213

G
Timebase timer counter
The timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the oscillation
clock (HCLK) as a count clock.
G
Counter clear circuit
The counter clear circuit clears the value of the timebase timer counter by the following factors:
• Timebase timer counter clear bit in the timebase timer control register (TBTC: TBR = 0)
• Power on reset
• Transition to main stop mode or PLL stop mode (CKSCR: SCS = 1, LPMCR: STP = 1)
• Switching the clock mode (from main clock mode to PLL clock mode, from subclock mode to PLL
clock mode, or from subclock mode to main clock mode)
G
Interval timer selector
The time interval selector selects the output of the timebase timer counter from four types.When
incrementing causes the selected interval time bit to overflow, an interrupt request is generated.
G
Timebase timer control register (TBTC)
The timebase timer control register (TBTC) selects the interval time, clears the timebase timer counter,
enables or disables interrupts, and checks and clears the state of an interrupt request.
CHAPTER 5 Timebase timer
195