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CHAPTER 3 CPU
3.8.5.2
Watch Mode
The watch mode operates only the sub clock (SCLK) and the watch timer.-The main
clock and PLL clock stop.
I Transition to Watch Mode
In the sub clock mode, when 0 is written to the TMD bit in the LPMCR register according to the settings of
the low-power consumption mode control register (LPMCR), the mode transits to the watch mode.
G
Data retention function
In the watch mode, data in the dedicated registers such as an accumulator and internal RAM are held.
G
Operation when interrupt request generated
When interrupt request generated with the TMD bit of the low-power consumption mode control register
(LPMCR) set to "0" the mode does not transit to the watch mode.If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed.If the CPU is ready
to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing
routine.
G
Pin state
In the watch mode, the input/output pins can be set to the high-impedance state or held in the state before
transiting to the watch mode according to the setting of the SPL bit in the low-power consumption mode
control register (LPMCR).
Notes:
• To set that pin to high impedance which serves either for a peripheral resource or as a
port in watch mode, disable the output of the peripheral resource, then set the TMD bit to
"0".Listed below are applicable ports.
This applies to the following pins:P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/
TOT0, P23/TOT1
• There is no sub-clock in MB90F897S.
138
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