Fujitsu MB90895 Series Hardware Manual page 420

CHAPTER 14 UART0
Reception and timing of flag set are shown in Figure 14.4-1.
Reception data
(operating mode 0)
Reception data
(operating mode 1)
Reception data
(operating mode 2)
SSR0 : PE, ORE, FRE
SSR0 : RDRF
: PE flag is disabled to detect in mode 1.
PE and FRE flag are disabled to detect in mode 2.
ST : Start bit
SP : Stop bit
A/D : Address/data select bit in operating mode 2.
G
Timing of receive interrupt request generation
With a receive interrupt enabled (SSR0: RIE = 1), when a receive interrupt request is issued when any one
of the receive data load flag (SSR0: RDRF), parity error flag (SSR0: PE), and overrun error flag (SSR0:
ORE) and framing error flag (SSR0: FRE) is set, reception interrupt is requested.
402
Figure 14.4-1 Reception and Timing of Flag Set
ST
D0 D1
ST
D0 D1
D0 D1
D5 D6
D7 SP
D6 D7 A/D
SP
D7
D4 D5 D6
Reception interrupt generating