Interrupts Of Can Controller - Fujitsu MB90895 Series Hardware Manual

16 bit, controller manual
Table of Contents

Advertisement

16.4

Interrupts of CAN Controller

The CAN controller has a transmit complete interrupt, receive complete interrupt and
node state transition interrupt, and can generate interrupts when;
• The transmission complete bit (TCR: TCx) is set.
• The reception complete bit (RCR: RCx) is set.
• The node status transition flag (CSR: NT) is set.
I Interrupts of CAN Controller
Table 16.4-1 shows the interrupt control bits and interrupt factors of the CAN controller.
Table 16.4-1 Interrupt Control Bits and Interrupt Factors of CAN Controller
Transmission/
Interrupt flag bit
Reception
Transmission
Transmission
complete bit TCR:
TCx=1
Reception
Reception
complete bitRCR:
RCx=1
Transmission
Node status
transition flag bit
CSR: NT=1
G
Transmission complete interrupt
When message transmission is completed, 1 is set to the TCx bit in the transmission complete register
(TCR).When a transmission complete interrupt is enabled (TIER: TIEx = 1) and when TCx = 1, a
transmission complete interrupt is generated.When a transmission request to the message buffer is set
(TREQR: TREQx = 1), the TCx bit in the transmission complete register (TCR) is automatically cleared to
"0".When "0" is written to the TCx bit in the transmission complete register (TCR) after the completion of
message transmitting (TCR: TCx = 1), the TCx bit is cleared.
G
Reception complete interrupt
When message reception is completed, "1" is set to the RCx bit in the receive complete register
(RCR).When a reception complete interrupt is enabled (RIER: RIEx = 1) and when RCx = 1, a reception
complete interrupt is generated.When "0" is written to the RCx bit in the reception complete register (RCR)
after the completion of message receiving (RCR: RCx = 1), the RCx bit is cleared.
Interrupt
Interrupt enable bit
factor
Message
Transmission complete
transmitting
interrupt enable bit
complete
TIER: TIEx=1
Message
Reception complete
receiving
interrupt enable bit
complete
RIER: RIEx=1
Node status
Node status transition
transition
interrupt enable bit
CSR: NIE=1
CHAPTER 16 CAN controller
Clear of the interrupt-request flag
Transmission request bit
Set TREQR: TREQx=1
Writing 0 to transmission complete bit (TCR:
TCx)
Writing 0 to reception complete bit (RCR: RCx)
Writing 0 to node status transition flag (CSR: NT)
533

Advertisement

Table of Contents
loading

This manual is also suitable for:

F2mc-16lx

Table of Contents