Fujitsu MB90895 Series Hardware Manual page 132

CHAPTER 3 CPU
Table 3.7-1 Functions of clock select register (CKSCR) (1/2)
bit name
bit9 CS1, CS0:
bit8 the multiplication rate
select bits
bit10 MCS:
PLL clock select bit
bit11 SCS:
sub clock selection bit
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The PLL clock multiplier is selected from among seven options depending on the combination of
PSCCR: CS2 and CKSCR: CS1/CS0.
Any reset causes the bit to return to the reset value.
Note:
When the PLL clock is selected (CKSCR: MCS = 0), writing is inhibited.To change the
multiplier, write 1 to the PLL clock select bit (CKSCR: MCS), update the multiplier select bits
(CKSCR: CS1, CS0), then set the PLL clock select bit (CKSCR: MCS) back to 0.
This bit indicates the main clock or PLL clock to be selected as the machine clock.
When the machine clock is switched from the main clock to the PLL clock (CKSCR: MCS = 1
the clock mode changes from main clock mode to PLL clock mode after the PLL clock oscillation
stabilization wait time is generated.The timebase timer is cleared automatically.The oscillation
stabilization wait time taken when the clock mode is switched from main clock to PLL clock is
fixed at 214/HCLK (about 4.1 ms during operation at an oscillation clock frequency of 4 MHz).The
oscillation stabilization wait time taken when the machine clock is switched from subclock mode to
PLL clock mode follows the values specified in the oscillation stabilization wait time select bits
(CKSCR: WS1, WS0).
Any reset causes the bit to return to the reset value.
Note:
1) When both of the MCS and SCS bits contain 0, the SCS bit supersedes the MCS bit,
thereby setting the subclock mode.
2) When switching from the main clock to PLL clock (CKSCR: MCS = 1
timebase timer interrupt enable bit (TBTC: TBIE) or interrupt level mask register (ILM:
ILM2 to 0) to disable timebase timer interrupts before writing 0 to the PLL clock select
bit.
This bit indicates the main clock or sub clock to be selected as the machine clock.
• When the machine clock is switched from the main clock to the subclock (CKSCR: SCS = 1 ->
0), the main clock mode changes to the subclock mode in synchronization with the subclock
(about 130 µs).
• When the machine clock is switched from the subclock to the main clock (CKSCR: SCS = 0 ->
1), the clock mode changes from subclock mode to main clock mode after the main clock
oscillation stabilization wait time is generated.Timebase timer is cleared automatically.
Any reset causes the bit to return to the reset value.
Note:
1) When both of the MCS and SCS bits contain 0, the SCS bit supersedes the MCS bit,
thereby setting the subclock mode.
2) If both the subclock select bit (CKSCR: MCS) and PLL clock select bit (CKSCR: SCS)
contain 0, the subclock is preferred.
3) When switching from the main clock to subclock (CKSCR: SCS = 1
timebase timer interrupt enable bit (TBTC: TBIE) or interrupt level mask register (ILM:
ILM2 to 0) to disable timebase timer interrupts before writing 0 to the subclock select bit.
4) The sub clock oscillation stabilization wait time (approximately 2 s) is generated at
power on or at cancellation of the stop mode.If the clock mode is switched from main clock
mode to subclock mode, therefore, the oscillation stabilization wait time is generated.
5) There is no sub-clock in MB90F897S.Set the initial value.
Function
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