Fujitsu MB90895 Series Hardware Manual page 133

Table 3.7-1 Functions of clock select register (CKSCR) (2/2)
bit name
bit13 WS1, WS0:
bit12 oscillation stabilization
wait time select bit
bit14 MCM:
PLL clock operation
flag bit
bit15 SCM:
sub clock operating
flag bit
These bits are used to select an oscillation stabilization wait time required for the oscillation clock
when the stop mode is canceled, when transition occurs from subclock mode to main clock mode,
or when transition occurs from subclock mode to PLL clock
• These bits are used to select one from four timebase timer outputs.
Any reset causes the bit to return to the reset value.
Note:
Set the oscillation stabilization wait time to an appropriate value depending on the oscillator
used.See 1.6.1 Reset Factors and Oscillation Stabilization Wait Times.
The oscillation stabilization wait time taken when the clock mode is switched from main clock
to PLL clock is fixed at 2
frequency of 4 MHz).When the CPU switches from subclock mode to PLL clock mode or when
it returns from PLL stop mode to PLL clock mode, the oscillation stabilization wait time
follows the values specified in these bits.
The PLL clock requires an oscillation stabilization wait time of at least 2
switching from subclock mode to PLL clock mode, therefore, set these bits to 10
The bit indicates the main clock or PLL clock currently selected as the machine clock.
• When the PLL clock flag bit (CKSCR: MCM) is "1" and the PLL clock select bit (CKSCR:
MCS) is "0", it indicates that the oscillation stabilization wait time of the PLL clock is currently
being taken.
The bit indicates the main clock or sub clock currently selected as the machine clock.
• When the subclock flag bit (CKSCR: SCM) is "0" and the subclock select bit (CKSCR: SCS) is
"1", it indicates that the machine clock is currently switching from subclock to main
clock.When the subclock flag bit (CKSCR: SCM) is "1" and the subclock select bit (CKSCR:
SCS) is "0", it indicates that the machine clock is currently switching from main clock to
subclock.
Function
14
/HCLK (about 4.1 ms during operation at an oscillation clock
CHAPTER 3 CPU
14
/HCLK. For
or 11 .
B B
115