Fujitsu MB90895 Series Hardware Manual page 200

CHAPTER 4 I/O PORT
output.
G
Operation in stop mode, timebase timer mode or watch mode
If the pin state specify bit (SPL) of the low-power consumption mode control register (LPMCR) is set to
"1" when the CPU operation mode switches to stop mode, timebase timer mode or watch mode, the pin
enters the high-impedance state.In this case, the output buffer is forcibly set to off regardless of the values
of the Port 4 direction register (DDR4).
Table 4.6-4 shows the state of the port-4 pins.
Table 4.6-4 The state of the port 4 pins
Pin Name
P40/SIN1 to
P44/RX
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
182
Normal
Sleep mode
Operation
General- General-
purpose I/O purpose I/O
ports ports
Stop Mode,
Timebase Timer Mode or Watch Mode
SPL=0
Input cut off, and
General-purpose I/O output becomes Hi-Z
ports (Pull-up resistor
disconnected)
SPL=1