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CHAPTER 10 8/16-bit PPG timer
I List of Registers and Reset Values of 8-/16-bit PPG Timer
Figure 10.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer
PPG0 operating mode control register
: H (PPGC1)
PPG0 operating mode control register
: L (PPGC0)
PPG0/1 count clock select register
(PPG01)
PPG0 reload register : H (PRLH0)
PPG0 reload register : L (PRLL0)
PPG1 reload register : H (PRLH1)
PPG1 reload register : L (PRLL1)
: Undefined
I Generation of Interrupt Request from 8-/16-bit PPG Timer
In the 8-/16-bit PPG timer, the underflow generation flag bits in the PPG operation mode control registers
(PPGC0: PUF0, PPGC1: PUF1) are set to "1" when an underflow occurs.If the underflow interrupts of
channels causing an underflow are enabled (PPGC0: PIF0, PPGC1: PIF1), an underflow interrupt request is
generated to the interrupt controller.
300
bit
15
14
13
12
0
0
0
bit
7
6
5
0
0
0
bit
7
6
5
0
0
0
0
bit
15
14
13
12
bit
7
6
5
bit
15
14
13
12
bit
7
6
5
11
10
9
8
0
0
0
1
4
3
2
1
0
0
1
4
3
2
1
0
0
0
11
10
9
8
4
3
2
1
0
11
10
9
8
4
3
2
1
0
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