Fujitsu MB90895 Series Hardware Manual page 566

CHAPTER 16 CAN controller
G
Starting receiving
To start receiving after the completion of setting, set the BVALx bit in the message buffer enable register
(BVALR) to "1" and enable the message buffer (x).
G
Canceling bus halt
After the completion of setting bit timing and transmission, write "0" to the HALT bit in the control status
register (CSR: HALT) to cancel the bus halt.
G
Processing when receiving completed
• If reception is successful after passing through the acceptance filter, the received message is stored in
the message buffer (x), "1" is set to the RCx of the reception complete register (RCR). For data frame
reception, RRTRx bit of the remote request receive register (RRTRR) is cleared to "0".For remote frame
reception, "1" is set to the RRTRx bit.
• If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt is generated.
• Process the received message after checking the completion of receiving (RCR: RCx = 1).
• Check the ROVRx bit in the receive overrun register (ROVRR) after the completion of processing the
received message.
- If the ROVRx bit is set to "0", the received message is enabled.When "0" is written to the RCx bit (a
reception complete interrupt is also cancelled), receiving is terminated.
- If the ROVRx bit is set to "1", a receive overrun occurs and the new message may overwrite the
received message.When a receive overrun occurs, write "0" to the ROVRx bit and then process the
received message again.
Above shows example of interrupt processing in the reception completion.
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