Table of Contents
Advertisement
CHAPTER 15 UART1
15.4.2
Generation of Transmit Interrupt and Timing of Flag Set
The transmit interrupt is generated when the serial output data register (SODR1) is
empty, and is in a state where the next transmitted data can be written.
I Generation of Transmit Interrupt and Timing of Flag Set
G
Set and clear of transmit data empty flag bit
The send data write flag bit (SSR1 register bit 11: TDRE) is set when the send data written to the serial
output data register 1 (SODR1) is loaded to the send shift register and the next data is ready for writing.The
send data write flag bit (SSR1 register bit 11: TDRE) is cleared to "0" when the next send data is written to
the serial output data register 1 (SODR1).
Transmission and timing of flag set are shown in .
[Operating mode 1, 2]
SODR1 writing
SSR1: TDRE
SOT1 output
[Operating mode 2]
SODR1 writing
SSR1: TDRE
SOT1 output
ST
D0 to D7
SP
A/D
G
Timing of transmit interrupt request
When a transmit interrupt is enabled (SSR1 register bit 8: TIE = 1), a send interrupt request is issued to
interrupt controller when the transmit data load flag bit (SSR1 register bit 11: TDRE) is set.
Note:
When sending is disabled during sending (SCR1 register bit 8: TXE=0: and also in operation
mode 1 (asynchronous multiprocessor mode), receiving disabled (also including bit 9: RXE)),
the send data write flag bit is set (SSR1 register bit 11: TDRF=1) and UART 1
communications are disabled after the shift operation of the send shift register stops.
The transmit data written to the serial output data register 1 (SODR1) before the transmission
stops is sent.
452
Figure 15.4-2 Transmission and Timing of Flag Set
Transmission interrupt request
ST D0 D1
Transmission interrupt generating
D0 D1 D2
: Start bit
: Data bit
: Stop bit
: Address/DAta select bit
Transmission interrupt generating
D7 SP
D5 D6
D2 D3
D4
A/D
Transmission interrupt generating
D6 D7
D0 D1 D2
D3 D4
D5
SP
ST D0
D1
D2 D3
D3 D4
D5
D6 D7
Advertisement
Table of Contents
