Fujitsu MB90895 Series Hardware Manual page 122

CHAPTER 3 CPU
I Correspondence of Reset Factor Bit and Reset Factor
Figure 3.6-6 shows the configuration of the reset factor bits in the watchdog timer control register (WDTC:
PONR, WRST, ERST, SRST).
Watchdog timer control
register (WDTC)
R Read only
W Write only
X Indefined
Table 3.6-4 Correspondence of Reset Factor Bit and Reset Factor
Generating power-on reset
Reset by watchdog timer
Input of external reset signal to RST pin
Software reset bit
*: The previous state is held.
X: Undefined
104
Figure 3.6-6 Configuration of Reset Factor Bit
bit7 bit6 bit5
PONR WRST
R R
Reset Factor
bit4 bit3 bit2 bit1
WTE WT1 WT0
ERST SRST
R R W W
PONR WRST
1 X
* 1
* *
* *
bit0
Reset value
X X X X X 1 1 1
B
W
ERST SRST
X X
* *
1 *
* 1