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CHAPTER 4 I/O PORT
G
Operation at reset
• When the CPU is reset, the value of the DDR2 is initialized to "0".Consequently, all output buffers are
set to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR2 is not initialized by reset. Therefore, when using port 2 as an output port, it is necessary to set
output data in the PDR2, and then set the bit in the DDR2 corresponding to the output pin to 1, and then,
to output.
G
Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high- impedance state.Because the output buffer is set forcibly to "OFF" irrespective of the value of the
DDR2.
Table 4.4-4 shows the state of the port 2 pins.
Table 4.4-4 The state of the port 2 pins
Pin Name
P20/TIN0 to
P27/INT7
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Note:
To set that pin to high impedance which serves either for a peripheral resource or as a port in
stop mode, watch mode, or timebase timer mode, disable the output of the peripheral
resource, then set the STP bit to 1 or set the TMD bit to 0. Listed below are applicable ports.
This applies to the following pins: P21/TOT0, P23/TOT1
172
Normal
Sleep mode
Operation
General-
General-
purpose I/O
purpose I/O
ports
ports
Stop Mode,
Timebase Timer Mode or Watch Mode
SPL=0
General-purpose I/O
Input cut off, and
ports
output becomes Hi-Z
SPL=1
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