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CHAPTER 3 CPU
I Mode Fetch
At transition to the reset operation, the CPU automatically transfers mode data and reset vectors by
hardware to the appropriate register in the CPU core. The mode data and reset vector are allocated to four
bytes of addresses "FFFFDC
oscillation stabilization wait time if generated), the CPU immediately outputs the addresses of the mode
data and reset vectors to the bus to input the mode data and reset vectors. This operation is called "mode
fetch". At completion of mode fetch, the CPU starts processing from the address indicated by the reset
vector.
FFFFDC
H
FFFFDD
H
FFFFDE
H
FFFFDF
H
Note:
The mode for reading mode data and reset vectors from internal ROM is set according to the
settings of the mode pins (MD0 to MD2). To use the mode pins in single-chip mode, set them
to the internal vector mode.
G
Mode Data
The mode data is used to set a memory access mode or a memory access area. It is allocated to address
"FFFFDF
mode register.
G
Reset vectors
The reset vectors are the start addresses of execution after completion of the reset operation. They are
allocated to addresses "FFFFDC
automatically by a mode fetch and transferred to the program counter.
Note:
This is hard wird reset vector on MB90F897/S.
See 19.6 Check the Execution State of Automatic Algorithm
102
" to "FFFFDF
H
Figure 3.6-4 Transfer of Mode Data and Reset Vectors
Memory space
Reset vector : bit 7 0
Reset vector : bit 15 8
Reset vector : bit 23 16
CPU mode data
". During the reset operation, this data is read automatically by a mode fetch and stored in the
H
H
". After a reset trigger event occurs (or after the lapse of
H
F
" to "FFFFDE
". During the reset operation, these vectors are read
H
2
MC-16LX CPU core
PC
PCB
Reset sequence
Micro ROM
Mode register
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