Table of Contents
Advertisement
CHAPTER 5 Timebase timer
Table 5.3-1 Functions of Timebase Timer Control Register (TBTC)
bit8
bit9
bit10
bit11
bit12
bit13
bit14
bit15
198
bit name
TBC1, TBC0:
These bits set the cycle of the interval timer in the timebase
Interval time select bits
timer counter.
•
•
TBR:
This bit clears all the bits in the timebase timer counter.
Timebase timer counter
When set to "0": All the bits in the timebase timer counter
clear bit
are cleared to "0".The TBOF bit is also cleared.
When set to "1": Disabled.The state remains unchanged.
Read: "1" is always read.
TBOF:
This bit indicates an overflow (carrying) in the time interval bit
Overflow interrupt
in the timebase timer counter.
request flag bit
When an overflow (carrying) occurs with interrupts enabled
(TBIE = 1), an interrupt request is generated.
When set to "0": The bit is cleared.
When set to "1": Disabled.The state remains unchanged.
Read by read modify write instructions: "1" read
Note:
TBIE:
This bit enables or disables an interrupt when the interval time
Overflow interrupt
bit in the timebase timer counter overflows.
enable bit
When set to "0": No interrupt request is generated at an
overflow (TBOF = 1).
When set to "1": An interrupt request is generated at an
overflow (TBOF = 1).
Unused bits
Read: The value is undefined.
Write: No effect
Reserved: reserved bit
Always set this bit to "1".
Function
The interval time of the timebase timer is set according to the
setting of the TBC1 and TBC0 bits.
One of four time intervals can be selected.
1)To clear the TBOF bit, disable interrupts (TBIE = 0)
or mask interrupts using the interrupt mask register
(ILM) in the processor status.
2)The TBOF bit is cleared at a write of "0", transition to
main stop mode or to PLL stop mode, transition from
subclock mode to main clock mode or to PLL mode,
transition from main clock mode to PLL clock mode, at a
write of "0" to the timebase timer counter clear bit
(TBR), or at a reset.
Advertisement
Table of Contents
